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NE1617A
All information provided in this document is subject to legal disclaimers.
?NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5  20 March 2012
20 of 30
NXP Semiconductors
NE1617A
Temperature monitor for microprocessor systems
 
[1]   The NE1617A does not include the SMBus time-out capability (t
LOW;SEXT
 and t
LOW;MEXT
).
[2]   Device operation between 3.0 V and 5.5 V is allowed, but parameters may be outside the limit shown in this table.
 
Table 15.   SMBus interface dynamic characteristics
[1]
V
DD
= 3.0 V to 3.6 V; T
amb
= 0 ?/SPAN>C to +125 ?/SPAN>C; unless otherwise specified.
[2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
IH
HIGH-level input voltage
STBY
, SCLK, SDATA
2.2
-
-
V
V
IL
LOW-level input voltage
STBY
, SCLK, SDATA
-
-
0.8
V
I
OL
logic output LOW sink current
ALERT
; V
OL
= 0.4 V
1.0
-
-
mA
SDATA; V
OL
= 0.6 V
6.0
-
-
mA
I
IH
HIGH-level input current
V
I
= V
DD
-1
-
+1
mA
I
IL
LOW-level input current
V
I
= GND
-1
-
+1
mA
C
i
input capacitance
SCLK, SDATA
-
5
-
pF
f
SCLK
SCLK operating frequency
0
-
100
kHz
t
LOW
SCLK LOW time
4.7
5.0
-
ms
t
HIGH
SCLK HIGH time
4.0
5.0
-
ms
t
BUF
bus free time between a STOP
and START condition
from SDATA STOP
to SDATA START
4.7
-
-
ms
t
HD;STA
hold time (repeated) START
condition
from SDATA START to first SCLK
HIGH-to-LOW transition
4.0
-
-
ms
t
HD;DAT
data hold time
from SCLK HIGH-to-LOW transition
to SDATA edges
0
-
-
ns
t
SU;DAT
data set-up time
from SDATA edges
to SCLK LOW-to-HIGH transition
250
-
-
ns
t
SU;STA
set-up time for a repeated
START condition
from SCLK LOW-to-HIGH transition
to restart SDATA
250
-
-
ns
t
SU;STO
set-up time for STOP condition    from SCLK LOW-to-HIGH transition
to SDATA STOP condition
4.0
-
-
ms
t
f
fall time
SCLK and SDATA signals
-
-
1.0
ms
Fig 6.    Timing measurements
P
S
SCLK
DATA
2  777
S
P
t
LOW
t
r
t
SU;STO
t
HD;STA
t
HD;DAT
t
f
t
SU;DAT
t
SU;STA
t
HIGH
t
HD;STA
t
BUF
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